Flip chip and wafer level packaging (WLP) technologies have become ubiquitous in recent years in applications from consumer and wireless devices to high-performance electronics. As requirements for high performance and reduced form factor grow, likewise the demands on these packaging technologies grow as well. A variety of high-end processes are employed for flip chip, wafer bumping, and WLP. These processes may include, for example, electroplating of metals, solder paste deposition, and dielectric formation using materials such as fluxes that need to be completely removed during the manufacturing process. Failure to completely remove these materials can result in contamination, yield loss, downstream problems in test and board level assembly, and reliability fallout in the field.
In the manufacture of electronic devices, solder is commonly applied to at least a portion of the solderable surface on articles such as, for example, integrated circuits (IC), surface-mount assemblies, flip chip assemblies, and the like, to provide a solder joint. For example, in the assembly of a flip chip assembly, one substrate having a plurality of solder bumps is attached face down onto another substrate. This attachment method may eliminate the need for first level IC packaging and provides a solution for system designs that are constrained by size, input/output (“I/O”) density, electrical performance (e.g., signal speed), reliability, or cost. Wafer bumping, or the reflow of solder into uniform ellipsoidal bumps, may be performed following the deposition of under-bump-metallurgy (UBM) and the deposition of the solder. Typical UBM consists of electroless nickel plated onto exposed aluminum, which is then followed by a protective layer of gold to prevent pad oxidation. Solder can then be deposited onto the plated pads using conventional photolithographic/vapor deposition techniques. More recently, solder paste has been deposited using stencil printing techniques with application tools such as squeegees or pressurized heads such as in an extrusion process.
The presence of an oxide on the solder surface can interfere with the reflow process. Consequently, surface oxides should be removed prior to reflow. The most common method for wafer bumping involves the use of an organic flux to reduce surface oxides. After flux is applied to reduce the surface oxides, subsequent packaging steps required to assemble flip chip devices include, for example, aligning the flip chip with substrate; reflowing solder under elevated temperature to create a bond; solvent cleaning to remove the flux (also referred to herein as “de-fluxing”); rinsing to remove residual solvent from cleaning; and under filling the flip chip.
Light emitting diode (LED) assemblies are packaged using similar wafer bumping and mounting methods as described above. After reflow soldering to bond the LED to the substrate, the substrate is cut into smaller sized components and mounted on the lead frame assembly using a solder paste that may have a flux contained therein. The de-fluxing step is typically performed using liquid or vapor phase solvents. Liquid phase de-fluxing may be performed, for example, using ultrasonic baths.
The solder joint in the flip chip assembly may be susceptible to defects such as crack growth and interfacial de-lamination. These defects can be attributed to stresses resulting from mechanical vibration and/or variation in ambient temperature leading to differential thermal expansion of the assembly. To remedy this, under fill materials, which are typically epoxy-based materials, are used to fill the gap between the flip chip and substrate around the solder joints thereby reducing stresses on the solder joint. In addition to reducing stresses on the assembly, under fill materials may also prevent corrosion of the solder joint through a sealing process. High adhesion of the under fill material to the substrate and die may be necessary to ensure reliability of the interconnect system.
Organic flux residues and/or solvent residues present on the surfaces of flip chip assemblies after wafer bumping or reflow soldering can affect the properties of the under fill material. The reliability of flip chip packages may be substantially reduced by flux/under fill incompatibility and/or by solvent/under fill incompatibility. Inadequate cleaning techniques can lead to inconsistent under fill flow patterns, void generation, and poor interfacial bond strengths. Typical failure modes include voids, filler striations, under fill de-lamination, under fill cracking, mechanical fatigue and corrosion. Corrosion-related failures can occur, for example, in the solder interconnect or in the substrate metallization. High temperatures, high humidity and reactive species (e.g., from the under fill or flux residues) can accelerate corrosion-related failures. Factors leading to poor performance of under fill materials include, but are not limited to, flux residues interfering with under fill flow and/or chemically reacting with the under fill; solvent residues from the cleaning steps interfering with under fill flow; and difficulties encountered with conventional methods of applying cleaning solvents in certain assemblies (e.g., assemblies having increasingly tight pitches or pitches of 200 microns (“μm”) or less, low standoffs or standoffs of 50 μm or less, and dense arrays of solder bumps).
Conventional wet processing methods may be inadequate to meet industry needs as technologies advance and as environmental restrictions increase. Among the limitations of conventional wet processing methods are the high cost and purity requirements of cleaning agents, progressive contamination of re-circulated liquids, re-deposition from contaminated chemicals, special disposal requirements, environmental damage, special safety procedures during handling, dependence of cleaning effectiveness on surface wet-ability to prevent re-adhesion of contaminants, and possible liquid residue causing adhesion of remaining contaminants. In addition, the International Technology Roadmap for Semiconductors has recommended a significant reduction in the use of water in various processing steps to prevent water shortages. Moreover, with the continuing trend toward increasing wafer diameters having a larger precision surface area, a larger volume of wet processing chemicals may be required to complete the fabrication process. Therefore, there is an increasing need to replace environmentally damaging fluxing and de-fluxing processes with more environmentally friendly processes and chemistries.
The above problems have driven the electronics industry to pursue fluxless surface reduction methods for wafer bumping and flip chip assembly. Such methods include surface reduction in reducing atmospheres (e.g., H2), laser ablation of oxides, and plasma techniques. However, the aforementioned processes present inherent economic and technical challenges. For example, some applications of hydrogen fluxless soldering may require high concentrations of flammable gas. Also, the melting or boiling points of oxide and base metal can be similar. It is not desirable to melt or boil the base metal during de-oxidation. Therefore, laser ablation processes are difficult to implement. Plasma techniques require expensive vacuum and electrical equipment, and create potentially damaging space charge and electromagnetic waves.